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Interface to Burst Flash Memories with Multiplexed Address and Data Bus

IP.com Disclosure Number: IPCOM000018572D
Original Publication Date: 2003-Aug-25
Included in the Prior Art Database: 2003-Aug-25

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Abstract

A conventional burst flash memory (e.g. Am29BDD320) has a certain number of pins that are shown in figure 1. The chip has three basic access modes: At first there is the mode for asynchronous read. When not configured for burst mode the flash memory is accessed by a microprocessor like a normal EPROM/SRAM, i.e. using CE#, OE#, A(19-0) to select the content to be read. This content will be available at pins DQ(31-0) some nano seconds later. This access type is also used for reading miscellaneous status information from the flash memory. Next there is the synchronous burst read mode which allows fast continuous data reads. The starting address at A(19-0) is latched into the flash memory on a rising edge of CLK when ADV# is active. After a short latency the data appears at pins DQ(31-0) and in subsequent cycles the memory will automatically increment the address and provide the read data cycle by cycle. So no further addresses have to be provided by the microprocessor.