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Low-pin-count SDRAM interface for 1000+ page teletext storage. Disclosure Number: IPCOM000018648D
Publication Date: 2003-Jul-30
Document File: 3 page(s) / 4M

Publishing Venue

The Prior Art Database



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Low-pin-count SDRAM interface

for 1000+ page teletext storage



Teletext is becoming a standard feature even in low-end TVs. As a result TV setmakers are no longer competing with the feature teletext, but with the number of pages that the TV stores internally, so they can be displayed without any waiting time. This feature requires about 10kbit of memory per teletext page that has to be stored. For more than 1000 pages the memory has to be more than 10Mb. This is too large to integrate economically. Using an external memory has the disadvantage that a lot of pins are required to connect it. This paper describes a way to drastically reduces the number of pins to connect an external SDRAM to a teletext processor.

Present solution

Presently SDRAMs are connected by a large number of pins that carry control, address and data information. A 64Mb memory with a 4-bit-wide data path typically has 27 functional pins that carry all this information. 64Mb of memory is enough to store 6000 pages of telextext.

The parallel interface allows a very high data rate. However, for teletext page storage a low data rate (ca 500kbits/s) is enough. So a serial interface would allow a significant reduction in the number of pins, without arriving at unrealistically high frequencies for the data transfer.

For FLASH memories a 3-wire SPI bus (serial peripheral interface) is sometimes used to connect to the processor. FLASH memory is unsuitable for teletext storage, as it is limited in the number of times data can be rewritten. SDRAM, unfortunately, is not sold with an SPI interface.

New solution

Fig. 1 shows a straightforward way to make a serial interface to an external DRAM. The control signals are connected directly form the processor to the memory. One data pin is connected to the input of an (external) shift register. The address data is shifted into the shift register. When it is fully loaded the control signals tell the SDRAM to read the address. After this the data transfer starts. During the data transfer time the SDRAM ignores the address inputs, so the fact that the shift register will output irrelevant addresses during this time does not affect the reliability of the data transfer. This approach reduces the number of pins to nine.

Fig. 2 show a way in which even more pins can be saved. In this approach instead of a shift register a so-called I2C bus expander is used. This a type of� IC that uses the 2-wire I2C bus to expand the number of I/O pins of an IC. As the I2C bus is too slow...