Publishing Venue
The IP.com Prior Art Database
Abstract
Disclosed is a method for stop clock third-droop removal. Benefits include improved functionality and improved performance.
Method for stop clock third-droop removal
Disclosed is a method for stop clock third-droop removal. Benefits include improved functionality and improved
performance.
Background
� � � � � Conventionally, power delivery for processors is based on a
transient event that only occurs when the processor comes out of a low-power
state with the clocks off. When the stop clock is asserted, all of the clocks
on the CPU turn on, and the CPU ramps back up to the highest ICC-signal level.
This change takes approximately 50 clock cycles. For a 2-GHz processor, the
duration is ~500 picoseconds. The voltage regulator module (VRM) responds in
approximately 15 microseconds. During this time, the capacitors on the
motherboard, package, and die run out of stored charge, and the voltages droop.
General description
� � � � � The disclosed method is stop clock third-droop removal. The VRM drives the stop-clock signal when it
adjusts its output for the transient event that occurs when the stop-clock
signal reaches the CPU. The VRM compensates and eliminates the third droop. The key elements of the method include:
• � � � � CPU
• � � � � VRM
• � � � � Stop-clock signal
Advantages
� � � � � Some implementations
of the disclosed structure and method provide one or more of the following
advantages:
• � � � � Improved
functionality due to enabling the VRM to send the stop-clock signal
• � � � � Improved performance
due to eliminating stop clock third-droop removal
• � � � � Improved performance
due to elim...