Browse Prior Art Database

Scalable Multiprocessor Invalidation Mechanism

IP.com Disclosure Number: IPCOM000018735D
Original Publication Date: 2003-Aug-04
Included in the Prior Art Database: 2003-Aug-04

Publishing Venue

IBM

Abstract

A Translation Look-aside Buffer (TLB) invalidate bus transaction is described to support a multiprocessor system that can accommodate processors with different sized virtual addresses. For example, this protocol allows for both 32-bit and 64-bit processors to be attached to the same system and be able to send and receive TLB invalidate commands between them to support systems that require the reclamation and reallocation of memory.