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Scalable Multiprocessor Invalidation Mechanism Disclosure Number: IPCOM000018735D
Original Publication Date: 2003-Aug-04
Included in the Prior Art Database: 2003-Aug-04
Document File: 1 page(s) / 45K

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A Translation Look-aside Buffer (TLB) invalidate bus transaction is described to support a multiprocessor system that can accommodate processors with different sized virtual addresses. For example, this protocol allows for both 32-bit and 64-bit processors to be attached to the same system and be able to send and receive TLB invalidate commands between them to support systems that require the reclamation and reallocation of memory.

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Scalable Multiprocessor Invalidation Mechanism

In symmetric multiprocessor systems, one processor at a time manages the page table memory. The processor that currently has authority to manage the page table memory is called the master processor. In some cases where the master processor is manipulating the page table (e.g. when the mapping of virtual to real addresses changes), the master processor must invalidate those pages from the subordinate processors' Translation Look-aside Buffers (TLB's). A special instruction is included in SMP-capable Instruction Set Architectures (ISA) to accomplish the TLB invalidates. In PowerPC BookE, this instruction is called TLBIVAX. TLB invalidate instructions operate with a Virtual address that searches the TLB (typically in a CAM fashion) to perform the invalidate. However, the buses that connect multiprocessors together operate with a real address (post translation). For the TLB invalidate instruction to invalidate the TLBs of subordinate processors, the virtual address formed by the TLB invalidate instruction needs to be broadcast to the other processors. In order to save I/O's, the virtual address is typically sent on the real address pins of the multiprocessor bus. However, the number of virtual address bits is usually larger than the number of real address bits (and real address pins). There are several methods available to solve this problem:

1. Broadcast only a portion of the virtual address and invalidate multiple pages per invalidate instruction so that the partial virtual address will fit on the real address pins.
2. Additional pins can be added to accommodate the virtual address broadcast.
3. Or some of the data bus pins can be used to broadcast part of the virtual address.
4. Or the virtual address can be broadcast on the same...