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Clock Tree Skew Fixing Algorithm Disclosure Number: IPCOM000018876D
Original Publication Date: 2003-Aug-19
Included in the Prior Art Database: 2003-Aug-19

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Colin MacDonald Anis Jarrar


Today’s Systems on Chip(SoC) integrated circuits (ICs) have a vast number of synchronous elements requiring clocking signals. The distribution of a clock signal to a large number of endpoints is typically accomplished through the construction of a clock tree network. Clock Tree Synthesis (CTS) and Optimization (CTO) tools are used to build clock trees according to supplied constraints such as clock insertion delay and maximum clock skew. Global clock skew is the largest time difference between the arrival times of active clock edges at any two endpoints on the clock tree. However, due to a number of different factors, it’s commonly not possible for the CTS/CTO tools to meet global clock skew targets. This article describes the incentives and difficulties in managing clock skew, and describes a Clock Tree Skew Fixing Algorithm [CTSFA] and methodology for meeting clock skew goals with a minimum number of changes to the original clock tree network.