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Method for determining the optimum number of power distribution vias in a package design Disclosure Number: IPCOM000019132D
Original Publication Date: 2003-Aug-29
Included in the Prior Art Database: 2003-Aug-29
Document File: 5 page(s) / 67K

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Disclosed here is a method to determine the optimum number, location and type of vias in a first or second level package design needed to ensure proper power distribution, proper signal current return and signal shielding at a minimum manufacturing cost.

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  Method for determining the optimum number of power distribution vias in a package design

Today's high performance packaging components, such as multiple layer ceramic chip carriers and Printed Circuit Boards (PCBs) require the design of a robust and reliable power distribution system that must have the following characteristics: It must have low impedance to deliver the increasingly large current demands of the active components, it must provide an adequate current return path for the high speed signals, and if deemed necessary, it can be used to provide electrical shielding for signals that are in close proximity. These design goals apply to the planar interconnections as well as the vertical interconnections using vias.

Focusing on the vertical interconnections of the power distribution system, a trivial solution that may achieve these goals is to use as many power distribution vias as the available area allows. In practice, design rules are typically defined that instruct the designer or CAD tool to reserve predefined locations for signals and power vias, and these rules can be used to verify that signals have a proper return path. However, as these desirable electrical characteristics always benefit if more power vias are present, there is an incentive to increase their number even if their benefit is marginal or negligible.

In the other hand, there is a per unit cost associated with manufacturing each via, as they have to be individually punched or drilled. Due to the increasingly competitive nature of the industry, there is also a strong push for reducing the number of vias used in order to reduce the component's cost. As a result, the problem of determining the minimum number of power distribution vias that will meet the component's electrical requirements arises.

Disclosed here is a method that addresses the optimization problem mentioned above. If it is applied to a completed design, it will flag vias that can be safely removed. If it is applied to a design in progress, it will indicate the locations were power vias need to be added in order to meet the desired performance requirements.

This is accomplished by scanning each signal via going through a give layer, and analyzing the area immediately surrounding it. It identifies where other signal and power vias are located, and applying a set of designs rules, identifies which power vias are needed for power distribution, signal return and shielding from other signals.

This is done on a layer by layer basis, in an automated form by a computer program or script:


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extract via geometry data, breaking it down by layer


set the current layer to process.

processed all Produce resultslayers?

 determine nearest power planes for connectivity of power vias

Determine vias needed for power delivery to active components and decoupling capacitors

Determine vias needed for connectivity to the BSM of the package


Set the current signal via to process

processed all vias?