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This invention is a solution for an RZ multi-level DAC offering a way to achieve better linearity and accuracy by choosing the best LUT configuration using a programmable, controllable LUT.
English (United States)
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Delta-Sigma Modulator with Calibrated Multilevel (RZ) Return to Zero Analog to Digital converter
The continuous-time delta-sigma modulator is a solution for high-speed, high-resolution A/D (analog-to-digital) converters.
Excess loop delay  (delay between the quantizer clock edge and the time when a change in output bit is seen at the feedback point in the modulator) degrades the performance of the delta-sigma modulator, since it's unpredictable and the right parameters can't be determined before manufacturing.
The way to make the circuit unaffected by the unknown excess loop delay is to use an RZ (return to zero) DAC (digital-to-analog converter) . The implementation of a two-level DAC is quite simple with differential logic.
The implementation of a multi-level DAC, which can help the implementation of a modulator with a lower sampling rate and a lower OSR (over-sampling ratio), is a harder task.
A previous invention presented a way to implement a delta-sigma modulator with an RZ multi-level DAC, assuming an RZ two-level DAC. A block diagram of the preceding architecture is as follows:
1/T sampler and A/D
Resonator or Integrator
Resonator or Integrator
Σ Σ Σ
G#1 G#2 G#3
Multi-level RZ DAC
RZ DAC #1
RZ DAC #2
RZ DAC #N
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The output of the A/D is the input to a LUT (look-up table). According to the A/D output (every sampling period), the LUT will divide the RZ DACs into three sets:
Set #1 - all the RZ DACs that will output negative RZ pulse. Set #2 - all the RZ DACs that will output positive RZ pulse. Set #3 - all the RZ DACs that will output zero pulse (this set is optional).
The LUT will choose those three sets (or two sets) in such a way that the output of the header will give the desired RZ multi-level pulse. A ver...