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Double mode receiver architecture for low-power digital data links with combined support for mulitlevel pulse amplitude modulation (4,5-PAM) and non-return-to zero (NRZ) coding with Decision-Feedback Equalization. Disclosure Number: IPCOM000019203D
Original Publication Date: 2003-Sep-04
Included in the Prior Art Database: 2003-Sep-04
Document File: 5 page(s) / 118K

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  Double mode receiver architecture for low -power digital data links with combined support for mulitlevel pulse amplitude modulation (4,5-PAM) and non-return-to zero (NRZ) coding with Decision-Feedback Equalization.

  Decision Feedback Equalizers (DFEs) are used to restore the attenuated signal at the receiving end of a band-limited channel. Due to their non-linear operation they exhibit better bit error rate performance when compared to feed-forward equalizers [1]. A basic implementation of a receiver using a DFE is given in Fig. 1, where the case of a two-tap decision-feedback equalizer is shown.

The outcome of the receiver is the sequence of digital symbols D[n] . The digital value (0 or 1) is multiplied by the tap coefficient h0 , and then subtracted from the analog imput signal. Similarily D[n+1] , which is the digital value delayed by one clock cycle, is multiplied by h1 and also subtracted.



Receiver input




T/H Delay (1 cycle)


Adder (analog)

Figure 1. Block diagram of receiver with 2-tap DFE.

The problem of this implementation is the delay in the feedback path: The signal must travel through the processing chain (track and hold, comparator, multiplication by h0 , subtraction) within one clock cycle. This is impractical for very high data rates.

A solution to this problem was proposed in [2], and is shown in Fig. 2 for the case of a single-tap decision feedback equalizer: Instead of slicing the analog value at level zero, two comparators are used with reference levels (Vref1, Vref2) shifted by +/- h0 . A differential signal constellation is assumed with the analog value ranging form -1 to 1. Hence, two digital values are delivered at the output from which only one is the valid decision bit. The previous symbol is then used to determine which comparator output is the correct data bit. Hence, by sampling with different reference levels at the same time, the need for a fast analog feedback can be avoided. In the case of a 2-tap DFE, four comparators are needed, and the last two symbols select one of the four digital comparator outputs as the valid symbol.



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Vref 1

Vref 2

Comparator 2

Previous bit

Figure 2. High-speed implementation of single-tap DFE.

Proposed Architecture

The proposed architecture is shown in Fig. 3. For the case of a 2-tap decision feedback equalizer, the analog sampling front end is a track-and-hold device, followed by four comparators with variable reference levels. The reference levels are set with digital-to-analog converters (DACs). Interestingly, this analog front-end is very similar to a multilevel PAM receiver. An n-PAM receiver needs (n-1) comparators to be able to...