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Disclosed is a method of improving error recovery and debug capability in a multi-ported memory controller.
English (United States)
This text was extracted from a PDF file.
This is the abbreviated version, containing approximately
58% of the total text.
Page 1 of 1
A method of improving error recovery and debug capability in a multi-ported memory controller
In the design being disclosed, distinct error indicator bits and an associated error address register is maintained for each port in a multi-ported memory controller. The error indicator bits consist of an uncorrectable ECC check indicator, a read data parity check indicator, a write data parity check indicator, an implemented memory check indicator, and a multiple error indicator. These error indicators are set by hardware and reset by software. If any of these indicators are set, an interrupt is routed to the microprocessor to service the error. It also indicates that the address of the access that caused the failure can be found in the error address register. The software interrupt handler then can use this information to properly service the interrupt and determine the proper remedy for the problem. In this interrupt handler it should reset the error indicators since the error address register can not be updated while any of these bits are set.
Otherwise, this would prevent the software interrupt handler from analyzing the very first cause of the error --- usually a key ingredient for understanding the source of the problem.. However, if another of these errors occurs while any of the error indicator bits are set, the multiple error indicator would be set. This is an indication that another error has been detected while processing the first error. In this case the ad...