Self-Calibrated MRAM Sense Amplifier
Publication Date: 2003-Sep-24
The IP.com Prior Art Database
The basic problem for sensing a 1T1MTJ memory cell is, that the signal is much smaller, than for a ROM or a Flash-EEPROM cell. Till now, resistance changes up to MR = 40 % have been reported (MR = (Rhigh – Rlow)/Rlow). During RD operation, the resistance change of the MTJ (stored value is 0/1, or Rlow/Rhigh) is sensed as a current or voltage change by the sense amplifier at the bit line of the memory array. For yield and speed considerations it is important to transform as much as possible of the resistance change into a current or voltage signal. In reality there is the problem, that due to non-idealities in the circuits, a certain amount of the signal is lost. This reduces RD speed and reliability of the memory. While the sources for offsets and signal losses can be contributed to a lot of circuit details of a sense amplifier, the result is always the same. Looking at the signals applied to the input of the sense amplifier and comparing the output, the whole circuit behavior can be described by an overall offset of the circuit. Usually a modeling is done by applying offset current or voltage sources at the input of the sense amplifier circuit. From precision analog circuits it is commonly known, that offsets can be reduced by sophisticated layout techniques and auto-zero techniques. In case of 1T1MTJ memories, the RD operation has to be done in a few ns. So standard offset compensation techniques are by far to slow in order cancel offset voltages during a RD operation in high-speed MRAM memories. Often these circuits need large chip areas and are not suitable for dense memory arrays. This document describes techniques to achieve maximal signal gain and sensing speed, by doing a calibration of the MRAM sensing circuits. Moreover, the circuits are small and therefore suitable for the use in memory designs.