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Output Buffer's Memory and Addressing Mechanism Disclosure Number: IPCOM000019781D
Original Publication Date: 2003-Sep-29
Included in the Prior Art Database: 2003-Sep-29

Publishing Venue



Disclosed is an electronic mechanism to generate read and write addresses for a dual port memory system. The memory buffers print head data for a five or ten beam printer. The data is written four bytes at a time in scan line order. The read operation removes data twenty bytes at a time (four from each of the five scan lines). This design allows for reading forty bytes at a time in ten beam mode by implementing memory to hold ten scan lines of print data.