Output Buffer's Shift Register and PQE Interface
Original Publication Date: 2003-Sep-29
Included in the Prior Art Database: 2003-Sep-29
Disclosed is an electronic mechanism for buffering data from a synchronous system and delivering it at very high speed to an asynchronous system. This mechanism responds to an asynchronous "read" signal to deliver data virtually instantaneously. It's architecture eliminates the usual requirement of synchronizing the asynchronous "read" signal to the system clock. It still has the advantage that the buffer memory and other control mechanisms are fully synchronous to the system clock.