Browse Prior Art Database

Output Buffer's Shift Register and PQE Interface Disclosure Number: IPCOM000019782D
Original Publication Date: 2003-Sep-29
Included in the Prior Art Database: 2003-Sep-29
Document File: 3 page(s) / 92K

Publishing Venue



Disclosed is an electronic mechanism for buffering data from a synchronous system and delivering it at very high speed to an asynchronous system. This mechanism responds to an asynchronous "read" signal to deliver data virtually instantaneously. It's architecture eliminates the usual requirement of synchronizing the asynchronous "read" signal to the system clock. It still has the advantage that the buffer memory and other control mechanisms are fully synchronous to the system clock.

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Output Buffer's Shift Register and PQE Interface


A typical data path for an IBM black-on-white high-end production printer will consist of three major sections.

1. An input buffer to receive the compressed print data from an input interface. This buffer is used to isolate the input interface from the decompressor. This enables higher data throughput since the input interface and the decompressor typically don't have to wait on each other since they can operate independently.

2. A decompressor to take compressed print data from the input buffer and perform the decompression function.

3. An output buffer to receive print data from the decompressor and an interface to transfer this data to the PQE (print quality enhancement) board. The buffer function is required for multi-beam printers because data are received and decompressed in scan line order but must be reordered before it is sent to the PQE board. The PQE board needs to simultaneously receive a byte from each beam's data stream. The output buffer also isolates the operation of the decompressor from the print head.

Prior Art

The decompressed data was typically saved into several asynchronous FIFOs (first-in-first-out memories). These FIFOs were grouped using two FIFOs for each beam. This operated by saving all the print data for an entire beam into a single FIFO. The next beam's data would be saved into the next FIFO and so on until all the data for a single sweep of the print head lasers was saved into these FIFOs. An additional bank of FIFOs was used for buffering so that data could be received and saved by one bank of FIFOs while data was being sent to the print head from the other bank of FIFOs. These banks of FIFOs operated in an alternating (ping pong) mode. Therefore, ten FIFOs were needed for a five-beam print head. Additionally, this asynchronous style of FIFO is rapidly becoming obsolete in favor of the newer synchronous style.

Design Challenges

This project presented several significant challenges in the scan buffer area.

An architecture supporting ten beams was required to insure a smooth transition to the upcoming 10-beam engines. Using current architecture would require using twenty asynchronous FIFOs.

It was desired to operate the data path in a synchronous fashion to enable higher data rates and better reliability. However, the input interface to the PQE board is designed to operate with asynchronous FIFOs. The data access time required would be very difficult to achieve. This is due to the asynchronous nature of the "read" signal with respect to the synchronous operation of the

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scan buffer. The PQE board will not be redesigned for this project. Therefore, this scan buffer implementation must work seamlessly with several versions of PQE board that are in the field.

This Disclosure

This scan buffer design offers novel solutions to these design challenges.

The PQE board issues a "read" signal when it needs data. This signal would be driven f...