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Intelligent Netlister – Providing a unique value proposition to chip designers Disclosure Number: IPCOM000019947D
Original Publication Date: 2003-Oct-13
Included in the Prior Art Database: 2003-Oct-13

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Sanjeev Mathur John Walters


In this complex world of chip design, connecting thousands of signals on a chip poses a unique challenge to designers. As time-to-market becomes more critical, companies are turning towards complex electronic design automation (EDA) tools, which can automate the design, verification, and layout of a chip. A critical starting point for these tools is a chip-level hardware description language (HDL) netlist, which defines the connectivity across various blocks on the chip. Automating the generation of this HDL file is essential in order for chip designers to improve their productivity and reduce the chip design cycle time. In response to this challenge, designers have developed a process for automating netlist generation using a GUI-based tool. Intelligent Netlister, as the tool is called, helps a user easily define chip-level HDL connectivity, irrespective of the levels of hierarchies involved in designing a chip.