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Shared PCI Host Bridge Access in a Clustered System Disclosure Number: IPCOM000020002D
Original Publication Date: 2003-Oct-16
Included in the Prior Art Database: 2003-Oct-16
Document File: 3 page(s) / 50K

Publishing Venue



Two central electronic complexes (CECs) share a PCI Host bridge attached to the two CECs through a common interconnect structure, such as a switch or IBM pSeries* High Speed Link (HSL) loop. Operating systems in each CEC share PCI adapters connected to the common PCI Host Bridge (PHB) using memory mapped IO. A memory mapped PHB doorbell register and message buffer facilitates both operating systems sharing the PHB configuration address and data register.

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Shared PCI Host Bridge Access in a Clustered System

  A computer system comprised of two independent operating systems in separate central electronics complexes (CECs) may be connected through a loop or switching fabric to a common PCI Host Bridge (PHB), as shown in Figure 1. Such a system may further include a PCI IO adapter connected to the common PHB and, for high availability purposes, the two operating systems may share this adapter. To accomplish such sharing, each operating system may then include a device driver capable of memory mapped IO through the common PHB to PCI memory facilities within the adapter memory. This is possible if the two operating systems duplicate the memory mapping from their respective processor addresses to the same PHB memory space. It is also possible when the two operating systems have different mappings from processor address space to the PHB memory space if the PHB can decode more than one processor address space to the same PCI address space.

    PCI device drivers also reference adapter PCI configuration space commonly utilizing a PCI standard methodology comprised of a configuration address and data register in the PHB. To perform a configuration read operation, the device driver stores the PCI configuration address of the target register in the PHB configuration address register and subsequently performs a load from or store to the PHB configuration data register to effect the associated PCI bus configuration red or write operation. Commonly, the platform firmware -- such as PC BIOS -- or operating system kernel provides a utility function so that device drivers do not directly access the PHB hardware and to serialize access to these PHB facilities between multiple device drivers running on the same CEC or within the context of the same operating system.

    To enable device drivers in each CEC to perform configuration IO to any adapter connected through a single, shared PHB requires that each CEC have exclusive access to the combination of PHB configuration and address register during the sequences of PHB register operations that effect a PCI configuration read or write. A hardware facility and platform firmware or operating system kernal protocol facilitates the two operating systems sharing a common PHB configuration and data address register, as illustrated in figure 2. In utilizing this facility and protocol, one CEC is designed the "primary CEC" and the other CEC the "alternate CEC". The role of the primary CEC is to serialize access to the common PHB configuration address and data register and to perform all configuration accesses for both operating systems. The alternate CEC utilizes the hardware facility and protocol to request the primary CEC to perform a configuration read or write on its behalf.

    The hardware facility includes a PHB register mapped in both CECs' processor address space and that is capable of generating an interrupt to the primary C...