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Method and Apparatus for Software Managed Coherency of Hardware Buffers

IP.com Disclosure Number: IPCOM000020052D
Original Publication Date: 2003-Oct-21
Included in the Prior Art Database: 2003-Oct-21

Publishing Venue

IBM

Abstract

An incomplete or incorrectly implemented cache coherency layer in hardware can often force an expensive or time-consuming hardware fix before it is useable. However, once the problem is identified it is possible for software to manage the coherency manually by forcing coherent writes through the cache as needed. This solution eliminates the need for a hardware change while keeping much of the original performance benefits of the caching architecture.