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A Controllable Method to Reduce Transistor Gate Feature Sizes Independent of Photolithography.

IP.com Disclosure Number: IPCOM000020200D
Original Publication Date: 2003-Oct-31
Included in the Prior Art Database: 2003-Oct-31
Document File: 4 page(s) / 34K

Publishing Venue

Motorola

Related People

Authors:
Olubunmi O. Adetutu Steven G.H. Anderson Yolanda Musgrove

Abstract

Rationale: Future CMOS require circuit transistor gate feature sizes to decrease with increasing technology generation. However, photolithography places a limitation on the rate of gate size decrease from generation to generation. Both the “trim” etch process and descum etch process have been utilized to further decrease the size of the gate features without further strain on photo.