Browse Prior Art Database

Modeling Contention and Float Circuit Conditions in Timing Analysis

IP.com Disclosure Number: IPCOM000020628D
Original Publication Date: 2003-Dec-05
Included in the Prior Art Database: 2003-Dec-05

Publishing Venue

IBM

Abstract

Static timing tools have historically only analyzed the timing of when devices drive nodes, however, there are conditions where the behavior of the circuit is dependent on when devices turn off. The static timing analysis tools would propagate transitions from the nodes inputs to outputs without considering that contention would invalidate the logic value, or that when a node floats, it would not immediately change states, but could slowly drift to the other state. This resulted in inaccurate timing of these structures. This publication describes method for using the turn off edges of devices to improve timing accuracy.