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DMA padding to improve packet latency

IP.com Disclosure Number: IPCOM000020986D
Original Publication Date: 2003-Dec-16
Included in the Prior Art Database: 2003-Dec-16
Document File: 2 page(s) / 41K

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Disclosed is a methods use DMA padding to improve packet latency

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 56% of the total text.

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DMA padding to improve packet latency

Today's adapters for PCI bus use either Memory Write, or Memory Write and Invalidate to transfer data to the host memory. In particular, adapters based on the value of the pci latency time to use memory write and invalidate to transfer multiple cache lines of data to the host memory to avoid DMA setup overhead. Since this scheme has to terminate the data transfer at the end of cache line, transferring data longer than one cache line may need two DMA transactions if data is not end at the cache line boundary. The setup delay due to the second DMA transaction can be very significant if the system uses 32-bit addressing and memory mapping to support more than 4Gbits of system memory. As a result, address translation takes more time. This problem is aggravated by the fact that PCI does not guarantee the adapter will get the PCI bus right away for each of the subsequent DMA transactions if the bus is shared with other devices.

An example of a PCI bus with three devices, A, B, and C is given below. The latency timer is long enough to handle 1,024 bytes of data; and the cache line is 64 bytes. To send 1,000 bytes to the host memory, the adapter can use memory write and invalidate to transfer 960 bytes in the first DMA, and use memory write to write the remaining 40 bytes in the second DMA. Thus, the total transfer time is: T1 + T2 + T3 + T4 + T5 + T6 + T7 + T8, where

T1 = First DMA setup by adapter A

T2 = First DMA transfer (960 bytes) by Adapter A

T3 = DMA setup by Adapter B

T4 = DMA transfer by Adapter B

T5 = DMA setup by Adapter C

T6 = DMA transfer by Adapt...