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THE USE OF A SACRIFICIAL POLYSILICON ETCH-STOP LAYER IN FORMING SELF-ALIGNED TRENCH FET

IP.com Disclosure Number: IPCOM000021025D
Publication Date: 2003-Dec-17

Publishing Venue

The IP.com Prior Art Database

Abstract

A spacer assisted self-aligned trench FET process producing devices having a trench depth of about two micro meters, a body-to-trench spacing of about three-tenths of one micro meter and a reduced number of expensive masking steps. The spacer is formed out of dielectric material (such as silicon dioxide or the like), and utilizes a sacrificial silicon etch stop layer (such as chemical vapor deposited poly silicon or the like).