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POST CODE IMPLEMENTATION USING LOW PIN COUNT BUS

IP.com Disclosure Number: IPCOM000021175D
Original Publication Date: 2003-Dec-31
Included in the Prior Art Database: 2003-Dec-31

Publishing Venue

IBM

Abstract

The post BIOS (Basic Input Output System) in a computer system puts out check point codes by writing them on to I/O Port 80 H. These checkpoint codes are used for debug purposes. These are particularly useful during BIOS development, and also at times when the systems lockup during boot time due to hardware problems. In the legacy systems the compatibility bridge, generally called the South bridge forwarded these I/O cycles on to the compatibility PCI slot. A PCI PostCard is normally used is such systems to monitor. With the recent trend of smaller rack mounted servers systems that do not support the compatibility PCI slot there has to be an alternative mechanism to monitor and see the check points. The design uses the Low Pin Count Bus ( LPC ) for decoding the I/O port 80 accesses and displays the checkpoints on the seven segment displays on the Motherboard.