Browse Prior Art Database

(PF/eDRAM#4/PM) OffChip Test/RA Disclosure Number: IPCOM000021238D
Original Publication Date: 2004-Jan-07
Included in the Prior Art Database: 2004-Jan-07
Document File: 4 page(s) / 81K

Publishing Venue



Currently, large embedded DRAM (eDRAM) arrays which incorporate Built-In Self-Test (BIST) are tested in a sequentially piecemeal fashion, e.g. one megabit at a time. Each group of patterns exercised on that 1Mb block contains retention pauses, requiring long test times and numerous testers. This approach is practiced due to limited on-chip redundancy logic and latch storage space to calculate and store the redundancy solution accumulated during the execution of the eDRAM BIST. This publication describes a method for incorporating Redundancy Allocation Logic (RAL) into a generic storage array, ideally located in the kerf area of a wafer.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 31% of the total text.

Page 1 of 4

(PF/eDRAM#4/PM) OffChip Test/RA

Background of Embedded Memory and Embedded Memory Test:

Historically, digital systems have been designed with discrete memory chips and logic processor chips. Combining logic and memory circuitry onto one single chip has led to significant improvements in system performance and cost. Semiconductor companies have been building SRAM macros into their logic designs for several technology generations. The most recent development in embedded memory has been embedded DRAM (eDRAM). Embedded SRAM was a technically straightforward breakthrough, as the SRAM circuitry is built via the standard logic process. Embedded DRAM required additional technological invention, since the fabrication of DRAM memory is significantly different than the fabrication of logic circuitry.

Whenever memory is embedded, test is a challenge. There is a long history of memory test development, and this evolution has taken place in a memory test environment. Memory testers have full-pin contact on the memory device, can perform memory writes and reads with numerous voltage and timing profiles, and can accumulate fails and perform bitfail mapping. Once a memory macro is embedded in a logic chip, that well-established memory test environment is lost.

To overcome these challenges, some semiconductor manufacturers choose to design test-specific microprocessors into their memory macros. These microprocessors can be programmed to perform Built-In Self-Test (BIST) of the memory. A BIST-based methodology implements a set of patterns (address sequences, data topologies, etc.) by initializing the BIST circuit, and applying thousands of clock cycles.

DRAM Retention Testing:

DRAM circuits are analog in nature. They are used in digital systems to store digital '0' and '1' logic values, but they store their data states in volatile capacitors. Time-constant discharge of such capacitors is inherent to DRAM storage cells. DRAM memories therefore require "refreshing" at periodic intervals. A DRAM cell's "retention time" is defined as the amount of time that can elapse before a DRAM cell loses its logic state. A DRAM technology specification will indicate, to the system designer, the maximum amount of time that can elapse before a refresh operation must be performed on the DRAM array.

At Manufacturing Test, DRAMs must be tested to ensure that all of the cells meet the retention time spec for that technology. The process for performing this testing is: write the DRAM array to a known data state, pause testing and allow the DRAM to sit idle for a duration of time that exceeds the retention time spec, read the data out of the array and compare it to the expected data - to ensure that no cells lost their data integrity.

DRAM Repair and Redundancy:


Page 2 of 4

DRAM memories are typically extremely dense - often containing millions of memory cells, or capacitors. Each of these cells has an associated transistor, which either isolates the capacitor from a cap...