(PF/eDRAM#4/PM) OffChip Test/RA
Original Publication Date: 2004-Jan-07
Included in the Prior Art Database: 2004-Jan-07
Currently, large embedded DRAM (eDRAM) arrays which incorporate Built-In Self-Test (BIST) are tested in a sequentially piecemeal fashion, e.g. one megabit at a time. Each group of patterns exercised on that 1Mb block contains retention pauses, requiring long test times and numerous testers. This approach is practiced due to limited on-chip redundancy logic and latch storage space to calculate and store the redundancy solution accumulated during the execution of the eDRAM BIST. This publication describes a method for incorporating Redundancy Allocation Logic (RAL) into a generic storage array, ideally located in the kerf area of a wafer.