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Clock Domain with common source synchronization Disclosure Number: IPCOM000021347D
Original Publication Date: 2004-Jan-16
Included in the Prior Art Database: 2004-Jan-16
Document File: 2 page(s) / 68K

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This disclosure publication describe a simple mechanism to synchronize data with different phases

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Clock Domain with common source synchronization

Circuit for Synchronizing Asynchronous Data

It is common that in a single IC, to have different blocks running at different frequencies and/or of going from one clock domain to another one. To solve these problems, there are several well known methods to synchronize the data between the two domains. This description is a particular case of such phenomenon. Indeed, it can occur that two blocks are actually running at the same clock frequency but with a different phase or with a multiple of the same frequency, as schematically illustrated in Figure 1. This can result of a difference between the 2 clock trees or can be caused by a clock division. In such conditions, it is common practice to consider both clocks as asynchronous, hence having to synchronize every signal that goes from one block to the other. The technique presented hereafter, can be used to cope with the clock domain change problem on this specific case. Instead of using a complex scheme of signal synchronization or a long FIFO buffer, a very simple circuit can be used according to the present disclosure. This circuit comprises 2 counters and 4 level of pipes. Now turning to Figure 2 which describes the block diagram of the circuit (let us assume data sent from the clock phase 1 to the clock phase 2). The first counter is running on the first clock phase, and the second counter is running on the second clock phase. The first counter is used as a pointer...