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Method for cascode bias in cascode emitter coupled logic circuits Disclosure Number: IPCOM000021480D
Original Publication Date: 2004-Jan-20
Included in the Prior Art Database: 2004-Jan-20
Document File: 2 page(s) / 81K

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Bipolar logic circuits implemented in low BVceo technologies require cascode devices to prevent device breakdown. Disclosed here is a method to bias the cascode devices without the use of an external bias generator circuit.

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Method for cascode bias in cascode emitter coupled logic circuits

In standard implementations of AND Cascode Emitter Coupled Logic (CECL) circuits, one switching npn transistor (Q4 in Figure 1) has a higher collector to emitter voltage than the other three switching devices (Q1-Q3). When using a low BVceo technology to implement the AND circuit, the collector to emitter voltage on Q4 is greater than BVceo of 1.8V causing Q4 to "breakdown", which is current generation within the device that can result in incorrect logic operation due to reduced differential output voltage.

One method of avoiding the problem is to use higher breakdown voltage devices for the bottom switch pair (Q3 & Q4 in Figure 1). However higher voltage devices are inherently slower and cause a reduction in the logic circuit switching speed. Also higher breakdown devices consume more area than the high speed/low breakdown devices.

A second method of avoiding the problem is to reduce Q4's collector to emitter voltage by adding a series cascode transistor. The cascode transistor's base is typically connected to a DC voltage reference provided by a Cascode Bias Generator circuit. The drawbacks of the Bias Generator circuit are that it dissipates power, and if a single DC voltage reference is used to bias cascode transistors in multiple logic circuits, then chip area is consumed by the metal distribution bus.

Two cascode transistors, Q6 and Q9 in Figure 2, are added to protect Q4, and are biased with...