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Method for chipset feature abstraction Disclosure Number: IPCOM000021519D
Publication Date: 2004-Jan-21
Document File: 3 page(s) / 41K

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Disclosed is a method for chipset feature abstraction. Benefits include improved functionality, improved performance, and improved reliability.

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Method for chipset feature abstraction

Disclosed is a method for chipset feature abstraction. Benefits include improved functionality, improved performance, and improved reliability.


         Conventionally, chipsets have devices that are invisible to the host operating system. These devices, are initialized by the system BIOS and are not programmed by the operating system (OS) or any OS-based device driver. In some instances, the platform chipset may support additional capabilities that can provide performance boosts to platform I/O devices. For example, a chipset direct memory access (DMA) engine can enable an I/O device to perform fast memory-to-memory copies without involving the host CPU. The DMA engine may be able to specify an address range on an I/O device as write combinable. These and other chipset capabilities may exist only on specific chipsets or even on specific versions of select chipsets.

         Conventionally, if any platform I/O device, such as a local area network (LAN) or small computer system interface (SCSI) adapter is required to program the chipset or use features provided by the chipset, it must do so using proprietary means. The client device hardware or device driver software must embed information about the specific chipset features to be able to use its services, which has several drawbacks. For example, the client application must be able to scan for and identify the presence, version, and capabilities of the chipset. The application must have the capability avoid the chipset errata and use workarounds. This functionality is cumbersome to develop, maintain, test, and debug. Client hardware and device drivers are typically shrink-wrapped. A single version must typically work on a large number of different types of platforms with and without the specific chipset that provides the additional features.

         Allowing multiple client I/O devices to use the chipset feature becomes very difficult. Multiple client I/O devices must negotiate for exclusive and coordinated access to specific chipset capabilities, such as the DMA engine. Client I/O devices must follow a protocol for acquiring/locking chipset resources before using them and releasing them when they are no longer required.

         Client I/O devices must function with OS plug-and-play and power management mechanisms. For example, the host OS may stop and restart a client I/O device with a different range of I/O resources due to a plug-and-play event. If the I/O device uses the chipset feature to map its I/O resources as write-combining, it must reprogram the ranges into the chipset. As another example, the OS may transition a client I/O device to a low-power state and return it to a high-power operating state. The client device must reuse the same chipset resources and not attempt to access a new set of resources. Alternatively, it could release and reacquire the chipset resources.

         If future versions of the chipset implement enhancements that change the programming interface, ex...