DC Scan Diagnostic Method
Original Publication Date: 2004-Feb-17
Included in the Prior Art Database: 2004-Feb-17
This article proposes a solution to the problem of testing and efficiently diagnosing DC (broken or stuck-at) scan chain defects and localizing these defects to a failing Shift Register Latch (SRL) or associated scan clock tree. This on-the-fly quick and accurate pinpointing of systematic and random circuit faults can be performed during the test process of most scan based designs.