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A circuit technique is discussed that allows for variable page sizes to be used in a CAM (Content Addressable Memory) without adding any additional stages of delay.
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Circuit Technique for Implementing Variable Page Sizes into a CAM
Disclosed is a circuit technique that allows multiple page sizes to be used in a CAM (Content Addressable Memory) without adding any additional stages of delay. Typically, a block of memory (page size) is accessed at a time. Different applications utilize different page sizes for optimal performance. Current circuit implementations that allow for mulitiple page sizes do so by adding an additional stage or stages, which impact circuit performance. In a CAM array, every entry's address value is simultaneously compared to see if an address of interest is contained in the array. Each bit of the address value is compared, where the address value represents a particular page size. By excluding certain bits from being compared, a different page size can be stored in the CAM array.
This disclosed technique requires one SRAM cell integrated with an inverter and a N-device for each page size being supported. When that particular page cell is written, the bits that are not needed to be compared are excluded from the "match_line". Therefore, several page sizes can easily be supported.
A page cell is inserted into the match_line where the bits to be excluded by that page size are. Multiple pages can be supported by inserting page cells as needed into the match_line. Figure 1 shows a typical CAM structure--each cell contains a pulldown device that will pull the match_line low when the cell is miscompared (the ma...