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Performance Enhancement For Single Partition System With An Hypervisor Loaded In High System Memory Disclosure Number: IPCOM000021963D
Original Publication Date: 2004-Feb-17
Included in the Prior Art Database: 2004-Feb-17
Document File: 1 page(s) / 36K

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Disclosed is a method significantly enhancing the performance of a single partition in a logical partitioning system.

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Performance Enhancement For Single Partition System With An Hypervisor Loaded In High System Memory

In a logical partitioning system, the hypervisor is normally loaded into system memory at physical address 0. Partition memory logical addresses are translated into the system physical addresses before being used since hypervisor is only dealing with physical address. This translating process incurs additional execution time to hypervisor calls dealing with logical addresses such as Page Table Entry (PTE) and Translation Control Entry (TCE).

*Starting with POWER5 PowerPC processor, hypervisor logical addressing is introduced into its execution environment. The Hypervisor Real Mode Register (HRMO) allows the hypervisor to be loaded at its desired logical address 0 while it is actually offset by HRM) in the physical memory. Once the hypervisor is physically loaded into near the top of physical memory. Physical memory will be available starting at the physical address 0 and contiguous. Under this arrangement, it is possible to have a logical partition whose memory logical addresses are one-to-one mapped into the same physical addresses. It is achieved by allocating and assigning this partition its memory requirement from physical address 0. Partition ID=1 will also be reserved for this unique partition.

When a hypervisor call is made from partition ID=1, the hypervisor immediately skips the normal logical-to-physical address conversion which involves a table look-up....