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Disclosed is a design for simplifying a Synchronous Dynamic Random Access Memory (SDRAM) controller by the exclusive use of the burst length equal to one option.
English (United States)
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Simplifying an SDRAM controller design by using burst length = 1 exclusively
A Synchronous Dynamic Random Access Memory (SDRAM) controller design must be capable of bursting data to the SDRAM in order to take full advantage of the available bandwidth. Typically this is accomplished with an integer number of burst read commands or burst write commands (i.e. burst length greater than one). However, if the total burst length required is not an even multiple of the burst length command or even if the total burst length required is itself less than the programmed burst length, then the SDRAM controller must also issue burst stop commands and in some cases assert the data mask (DM) signal to the SDRAM to terminate such a burst. This introduces additional complexity into the design which can easily introduce logic defect(s) which may elude detection until late in the design cycle. This can add delay into the design cycle and ultimately delay the availability of the SDRAM controller.
This design approach solves this problem by executing all SDRAM read and write commands with the burst length equal to one option. Thus, by definition there is no required burst length that is not a multiple of the programmed SDRAM burst length. Therefore the burst stop command is never required to be issued nor is the data mask (DM) required to be asserted. This design does require that a SDRAM read or a SDRAM write command be transmitted during every cycle that data is to be transferred to/from the SDRAM. These commands require an address be sent with each command. However, the SDRAM command bus is an under-utilized bus and thus is available for this purpose. It is actually simpler for the har...