Browse Prior Art Database

Verification of Bus-structures with varying bit lengths using the Method of Length Adaptive Shift. Disclosure Number: IPCOM000022116D
Original Publication Date: 2004-Feb-25
Included in the Prior Art Database: 2004-Feb-25

Publishing Venue



Disclosed is a method for the verification of a chip design with a bus structure consisting of signals of varying bit length, or signals with both meaningful and non-meaningful data bits, where only the meaningful data is stored in a proper sequential order. This method is applicable to designs whose verification require tracing data over time and storing this data in a predetermined format for concurrent or post-process checking.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 40% of the total text.

Page 1 of 10

Verification of Bus-structures with varying bit lengths using the Method of Length Adaptive Shift.

Memory as Trace array : The memory as a trace array is conceptually depicted in Figure 1 with each row containing the data traced that cycle.

Software Trace Array: A two dimensional array is defined to model the Trace Array. As each software cell is defined of type unsigned long int(32 bits), the entire trace array row is covered with 52 cells.This is again conceptually shown in Figure 2.

The Problem: The software models of a design's signals are called facilities. The facilities to be traced are of varied lengths. Moreover, in some cases, only a part of the facility has to be traced.When a facility value is retrieved from the Hardware Model, it is usually stored in variables of type unsigned long int. Hence, in most of the cases, only a part of the variable has meaningful data. For e.g: When the hardware facility PROC_ICURDSIZE(0:3) is read from the model and stored in the local variable, from the trace array update point of view, other than the right most 4 bits, all other bits are unwanted (Figure 3). Due to this reason, a simple concantenation function will not help in building a valid Software Trace Array row. The extraneous bits have to be gotten rid of and concantenate only the valid bits in the correct and sequential order to map in exactly with the Hardware Trace Array.

Classical Solution: The Classical solution would be to manually hard-code each of the signals to be traced, in the correct sequntial order, into the Software Trace Array cells. This method would pose numerous problems :
(1) If the order or the length of the signals are changed, it would be a big problem to re-code the entire row.
(2) Same is true if new signals are added or old ones removed.
(3) Manual coding is highly error prone.

All these reasons urged the need to come up with a method, where the signals to be traced are fed into a file, in the correct sequence, with its actual length and the range to be traced, specified. This file should also contains a variable which specifies the number of signals to be traced. It is from this file that the Software Trace Array should be built!

The Invention: During every simulation run, a data structure is created, which contains the value, length and range of the signal to be traced in the correct sequence. This data structure is initialized by reading from the file during the Start Phase of the simulation run. For e.g:

Struct sigs{

Unsigned long int *data; Unsigned long int data_length_to_trace; Unsigned long int actual_length_of_fac, range1, range2;



Page 2 of 10

Struct sigs *trace_signals;

After intialization, trace_signals[0] contains the information of the first signal defined in the file and so on for the total number of signals specified in the file. This data structure is then used to build up the Software Trace Array, whenever required, using the Length Adaptive Shift Method.

The Length Adaptive Shift Meth...