Verification of Bus-structures with varying bit lengths using the Method of Length Adaptive Shift.
Original Publication Date: 2004-Feb-25
Included in the Prior Art Database: 2004-Feb-25
Disclosed is a method for the verification of a chip design with a bus structure consisting of signals of varying bit length, or signals with both meaningful and non-meaningful data bits, where only the meaningful data is stored in a proper sequential order. This method is applicable to designs whose verification require tracing data over time and storing this data in a predetermined format for concurrent or post-process checking.