Browse Prior Art Database

Self Tuning Firmware Algorithm For Allocation of I/O Address Translation Tables Disclosure Number: IPCOM000022478D
Original Publication Date: 2004-Mar-17
Included in the Prior Art Database: 2004-Mar-17
Document File: 1 page(s) / 49K

Publishing Venue



A computer system having indirect address translation tables for I/O has suboptimal memory utilization for these tables if the address translation tables are allocated based on maximum allowable I/O configurations. Allocation of address translation tables based on installed memory sizes produces better memory utilization for translation tables.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 1

Self Tuning Firmware Algorithm For Allocation of I /O Address Translation Tables

The current algorithm for IBM iSeries* eServer* systems for allocating address translation tables allocates a default size of translation table space per I/O hub chip. The size of the translation table is based upon the maximum amount of expansion I/O towers that could be attached to that I/O hub. This algorithm is very wasteful, as customers rarely attach the maximum amount of expansion I/O to a single I/O hub. Systems with small memory configurations would never support large I/O configurations, however enough translation table space would be allocated to support the maximum I/O configuration per I/O hub, and would consume a large percentage of total platform memory.

     This invention solves the problem of allocating too much address translation table space on platforms with small memory configurations. This invention is comprised of an algorithm to allocate address translation table space based upon the total platform memory size. Allocation of Translation Control Entry (TCE) tables must be done by Global Firmware (GFW) prior to the hypervisor instructions starting because special registers in the processor which has affinity to a GX adapter (I/O hub, or SMA-3 adapter) must be set to indicate the starting address and size of the TCE tables. These registers are used by the hardware to snoop the I/O bus fabric for memory access to these memory ranges, and inform the I/O bridge hardware to invalidate their local cached copy and retrieve a current copy from main storage. Since GFW is not aware of the external I/O configuration of the platform, a guess must be made as to how much TCE table space will be needed by the I/O hardware attached to a given I/O hub chip.

     GFW is aware of the memor...