Dismiss
The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Makefile generation for mixed HDL design

IP.com Disclosure Number: IPCOM000022642D
Original Publication Date: 2004-Apr-25
Included in the Prior Art Database: 2004-Apr-25

Publishing Venue

Siemens

Related People

Other Related People:

Abstract

An important function within the "Inway design system" of Infineon Technologies AG is makefile generation for RTL (Register-Transfer-Level) design. Especially for large designs the makefile concept (known from software development) reduces compile run times for various tools by not compiling all source code again after small code changes. Today, mixed HDL (Hardware Description Language) design gets more and more important. A smart algorithm for the generation of mixed HDL makefiles enables more efficient processing (compiling) of such mixed HDL designs. Support for new HDL's can be added in a relatively easy way. Up to now VHDL (Very High Speed Integrated Circuit Hardware Description Language) and Verilog (like VHDL, a hardware description language used to design and document electronic systems) were processed separately for certain tasks within Inway. Two separate makefiles are used for two separate compilation runs. The VHDL part does not know about the Verilog part and vice-versa. Depending on the makefile generator in use, a sandwich structure is even not supported. Missing or incorrect design parts are detected at late stage.