Browse Prior Art Database

MEMORY PARITY CHECKING Disclosure Number: IPCOM000022868D
Original Publication Date: 1976-Mar-31
Included in the Prior Art Database: 2004-Mar-27
Document File: 2 page(s) / 219K

Publishing Venue

Xerox Disclosure Journal


In a memory system having a plurality of memory modules 10, 12, 14, 16 each holding a portion of a single memory word 18a, 18b, l8c, l8d, respectively, a parity bit in each module is computed, at the time of storage, based on the parity of the next adjacent word portion. That is, parity bit 20a is the parity bit associated with word portion 18b, bit 2Db is associated with word portion 18c, bit 20c with word portion 18d and bit 20d with word portion 18a,