Browse Prior Art Database

Original Publication Date: 2004-Mar-29
Included in the Prior Art Database: 2004-Mar-29
Document File: 4 page(s) / 77K

Publishing Venue



This article describes a camera interface suited for allmost all types of CMOS image sensors. With just a four state Finite State Machine all synchronization and data processing are performed.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 49% of the total text.

Page 1 of 4


The improved universal camera interface (UCI) unit described herein allows the connection to almost all commercially available image sensing devices, such as cameras, because it is based on their common similarities. As a consequence, it makes the design of the color & format converter attached to the camera much easier. The improved UCI unit is built around a finite state machine (FSM) having four states which operates as the unit controller. Not only the pixel data from the active video area are forwarded to the next converter through a simple interface, but even more, the protocol errors are detected. By using the same events (which control the jump from one state to another, the line/pixel counters and the comparators are also controlled to check if the received image size is compliant to the expected format.

    Figure 1 shows the improved UCI unit referenced 10. Now turning to Figure 1, unit 10 comprises the master clock generator 11, configurations registers 12 and a data processing and synchronization circuit 13 that drives the color & ; format converter 14 as standard. The improvement lies in the implementation of a four state FSM controller in circuit 13 which will be described in more details by reference to Figure 2. It is to be noted the reduced set of IOs needed by this unit, one pin being shared between different types of cameras. The camera producing a start of frame (SOF) control signal works with the master clock (MCLK) delivered by the camera. All the camera output data & control signals are synchronized to this clock and the unit runs with the same master clock. For a camera compliant to the CCIR 656 standard, the SOF, VSYNC and HSYNC are not used and the unit runs with the camera own clock (PIXCLK). Data sent by the camera (not shown) are applied to circuit 13 as standard.

    This Universal Interface is principally composed of a Finite State Machine, 2 counters, comparators and a data decode unit.

    As shown in Figure 2, the FSM is composed of only four states, referred to as INIT, RESET, VSYNC and HSYNC. The FSM controls the counters and comparators in circuit 13 and validates the active pixel data (PIX_D) for the converter 14 by means of just one control line 'Data_Valid'. Operation of the FSM works as described below:
1. FIRST STATE: RESET At System Reset the FSM enters into the RESET state. There it waits until a Start of Frame (SOF) is detected on the interface input pin or a timing code Vertical End of Active Video (VEAV) has been decoded by the Control Word Detection block in case the timing controls are embedded within the video stream. The selection of the type of data stream is made by a configuration bit. In case the sensor timing signals are not pulses but are envelops, the next state will not be the INIT state but directly the VSYNC state.
2. SECOND STATE: INIT When a SOF pulse or a VEAV pulse has been detected in Reset, the FSM enters into the INIT state. This state...