Disclosed is a method that uses eutectic solder die bumps on the bump-less substrate C4 interconnects. These bumps are printed solder die bumps, rather than plated for the current high lead die bump application. Benefits include eliminating the reflow process and the bump formation module.

Background

The following are problems associated with the current state of the art process:

§         High substrate cost per unit. The bump formation process and required materials keep costs high. Current improvements include direct and indirect material sourcing.

§         Inherent interconnect issue. “Opens” due to misalignment and marginal bump volume on either the die or substrate bumps, and bump bridging-related shorts due to minimized spaces on misaligned bumps. Current improvements include flip chip assembly process optimizations within the chip attach module, and the supplier bump printing process.

§         Underfill quality issue. Voiding on the epoxy underfill and micro-cracks due to stress from the underfill matching property. This remains marginal on interactions with other packaging materials.

§         Die delamination. Due to an insufficient interconnect profile. This remain marginal on the total package design.

Figures 1 and 2 show a cross section of a standard wafer die to substrate. The end product of the present state of the art is achieved by melting the eutectic substrate bump to obtain the interconnection.

General Description

The disclosed method uses die bumps only, as oppose to a two-bump interconnect, and is the first step in eventually enabling a bump-less substrate technology. Figure 3 shows the eutectic solder die bump formation, enabling the connection to a bump-less substrate. Fi...