FIELD SHEILD FOR REDUCTION OF PARASITIC PERIPHERAL CAPACITANCE IN MOS DEVICE
Original Publication Date: 1980-Dec-31
Included in the Prior Art Database: 2004-Apr-02
Xerox Disclosure Journal
For maximum sensitivity in a,n MOS circuit, including a charge-detection circuit, the capacitance of the sense transistor gate (node) must be minimized. An important contribution to the capacitance is the peripheral capacitance formed where the node dopant meets the field implant in the self-aligned field im plan t/oxide process.