Browse Prior Art Database

HARDWARE IMPLEMENTATION OF 4-PIXEL CODE ENCODER

IP.com Disclosure Number: IPCOM000024529D
Original Publication Date: 1980-Oct-31
Included in the Prior Art Database: 2004-Apr-02

Publishing Venue

Xerox Disclosure Journal

Abstract

There is a need in electronic systems for compacting data so that the information contained within said data may be stored in less memory or transmitted at a higher rate. A problem with a simple run-length encoder is that it must process each input bit as it is received. To speed up the data rate, the run-length encoder may be designed to process data bits in parallel. The parallel processing of data in the form of data blocks increases the data rate, but ultimately a limit is reached based on the number of bits per block, which must be optimized for the particular application, and the circuit complexity, whicb must be minimized. An example of a commerically useful encoder is one that can operate in excess of 50 M bits per second in the compression of image data.