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A SENSOR ARRAY CONFIGURATION USING SINGLE SHIFT REGISTER

IP.com Disclosure Number: IPCOM000024715D
Original Publication Date: 1981-Oct-31
Included in the Prior Art Database: 2004-Apr-02

Publishing Venue

Xerox Disclosure Journal

Abstract

A configuration for implementing an image Read Bar using Silicon Integrated Circuits Technology with NMOS or CCD processing is shown in the drawing. There the photosites 5, which are photodiode type for higher responsivity, are close to the edge 6 of substrate 7 for lensless implementation. Only shift register 8, which can do the job of shifting the charge packets to the output amplifier 9 because the center-to-center spacing of the photosites 5 in full width arrays is about 50pm, is required. Completely NMOS processing is possible if bucket brigade implemen-tation is used. Each array length can be 0.5 to 1.5" long and a number of such arrays can be butted together on a ceramic substrate.