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ASYNCHRONOUS CHARGE-COUPLED DEVICE IMAGER (CCD) ARCHITECTURE

IP.com Disclosure Number: IPCOM000024716D
Original Publication Date: 1981-Oct-31
Included in the Prior Art Database: 2004-Apr-02

Publishing Venue

Xerox Disclosure Journal

Abstract

The conventional architecture of a Charge-Coupled Device (CCD) imaging chip 5 of the type used with raster image scanning systems is shown in Figure 1. The CCD 5 normally integrates the irradiance on the photosites 6 during the integration time, then transfers the generated electrons to an on board shift register 7. During the next integration period, the CCD shift register 7 shifts out the serial data while the photosites 6 are accumulating a new charge. To operate the CCD's at the maximum allowable speed, the integration time is made equal to the time required to empty the shift register 7. This allows the photosites 6 to integrate for the maximum allowable time, taking advantage of all the possible irradiance. This scheme also allows the CCD shift register 7 to shift out over as long a period as possible, providing minimum data rate for the integration time used. These capabilities are important where the CCD is scanning objects at high speed. It also means, however, that the CCD must be operated in a synchronous fashion, i.e., for a constant integration time, the shift register must be clocked at a constant rate.