PASS-THROUGH WITH GAIN
Original Publication Date: 1984-Feb-29
Included in the Prior Art Database: 2004-Apr-04
Xerox Disclosure Journal
This invention relates to an improved polycell chip design technique for automatic-ally placing logic elements (cells) and optimally routing their interconnects (lines). In a concurrent disclosure ("Polycell Place and Route Technique") it was proposed to provide the cell in two parts, viz. a logic function and an expandable buffer driver. The auto place and route computer program would select and increase the size of the buffer driver in proportion to the length of the interconnect line in order to achieve a uniform intercell signal propagation time.