HARDWARE ARCHITECTURE FOR RESOLUTION CONVERSION USING AREA MAPPING
Original Publication Date: 1993-Oct-31
Included in the Prior Art Database: 2004-Apr-06
Xerox Disclosure Journal
A parallel hardware architecture for implementing an area mapping technique used in the resolution conversion of images is disclosed. Typically, the computational burden of resolution conversion techniques in software impedes their use in real time image output terminals (IOTs). The disclosed hardware implementation, however, enables real time resolution conversion of images on most IOTs. The hardware architecture uses a transformation matrix to characterize the transfer function between an input resolution and an output resolution. The transformation matrix is composed of a relatively small number of non-zero entries that are made up of weighted values that are applied to input pixels to derive output pixels. Common resolution conversions are calculated using only a small number of transformation matrices (commonly only two). In essence, transformation matrices map the conversion of input scan lines to output scan lines, where the matrix values or weights form a set of values that repeat throughout an image. For computational efficiency, the transformation matrix can be represented using a systolic array. The disclosed architecture is characterized by a synchronous data flow with parallel processing. Additionally, the architecture has a unique method of handling a plurality of conversions at different input and output resolutions, the conversion being either interpolation (increase in resolution) or decimation (decrease in resolution).