DUAL ARBITERS FOR EFFICIENT BUS ARBITRATION
Original Publication Date: 1994-Feb-28
Included in the Prior Art Database: 2004-Apr-06
Xerox Disclosure Journal
Large digital system incorporating different VLSI chips (e.g., CPUs, DMA Controllers), which may each become a bus master, may introduce arbitration delays that reduce the overall bandwidth of a bus. Furthermore, the lack of consistency in chip manufacturers bus requestlgrant and clocking schemes only exacerbat the problem. Standard bus requestlgrant facilities provided by many of the devices result in idle time on the system bus while the new master synchronizes to the latest bus grant received. For example, in some direct memory access (DMA) applications, where only a few bytes are transferred per DMA request, the idle arbitration time can be as great as the time taken to perform the transfer.