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A SILICON JUNCTION FIELD EFFECT TRANSISTOR WITH A MODIFIED GATE FOR USE IN A CMOS PROCESS WITH NEGATIVE AND POSITIVE POWER SYSTEMS

IP.com Disclosure Number: IPCOM000027270D
Original Publication Date: 1996-Feb-29
Included in the Prior Art Database: 2004-Apr-07

Publishing Venue

Xerox Disclosure Journal

Abstract

In order for a JFET to function properly it must be reverse biased. This means that a single JFET can not have a negative voltage on the source and a positive voltage on the drain, or conversely, a positive voltage on the source and a negative voltage on the drain. If a JFET is biased using either a negative voltage on the source and a positive voltage on the drain or a positive voltage on the source and a negative voltage on the drain either the gate-source junction or the gate drain junction will become forward biased and the JFET will not operate correctly. A modified gate has been designed to allow negative to positive voltages across a single JFET. Additionally, this new JFET can handle voltages greater than 5 volts and is suitable for high voltage applications. This new JFET can also be used with standard CMOS cell libraries with the introduction of a p-well module.