Browse Prior Art Database

MATE: Micro Assist Thread Engine

IP.com Disclosure Number: IPCOM000027405D
Original Publication Date: 2004-Apr-07
Included in the Prior Art Database: 2004-Apr-07
Document File: 2 page(s) / 104K

Publishing Venue

IBM

Abstract

We disclose POWERmate, an asynchronous PowerPC assistive processing facility based on a threading infrastructure. Using the the assistive thread facility, asynchronous threads can be executed in multiple thread contexts on a single (or multiple) processor cores. The POWERmate facility is based upon 3 primitives: (1) a thread spawn instruction, (2) additional architected processor contexts, and (3) optional inter-thread register copy facility to transmit data between at least a first and a second thread.

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MATE: Micro Assist Thread Engine

We disclose POWERmate, an asynchronous PowerPC assistive processing facility based on a threading infrastructure. Using the assistive thread facility, asynchronous threads can be executed in multiple thread contexts on a single (or multiple) processor cores. The POWERmate facility is based upon 3 primitives: (1) a thread spawn instruction, (2) additional architected processor contexts, and (3) optional inter-thread register copy facility to transmit data between at least a first and a second thread.

The purpose of the MATE facility is to use the thread infrastructure present in today's high-performance processors to provide asynchronous processing, while reducing the synchonization overhead inherent in traditional SMT processing. In previous processing styles, media processing could be achieved using a dedicated graphics engine, SMT facilities, additional processors, or attached assist processors.

Micro-assist threads are preferably a feature enhancement added to a processor supporting SMT processing. As such, the processor will support multiple execution contexts, including architected registers for multiple contexts. The main extension to such a base processor consists of a new architected instruction to start a thread in one of the SMT contexts, specifying a starting address, and, optionally, an architected processor state to be transferred to that thread as an initial state.

In one mode of operation, this infrastructure is used to implement asy...

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