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Disclosed is a method that uses a circuit for a 5V tolerant I/O input buffer, which separates the propagation path of the high and low voltages and protects the MOS devices without noise margin impacts.
English (United States)
This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately
70% of the total text.
Input Buffer Circuit for High Voltage
Tolerant I/Os Using Low Voltage Tolerant Transistors
Disclosed is a method that uses a circuit for a 5V tolerant
I/O input buffer, which separates the propagation path of the high and low
voltages and protects the MOS devices without noise margin impacts.
To design the 5V tolerant I/Os, three main problems must be
Overstress of the MOS devices must be avoided.
Leakage from the pad pin must be avoided.
Input noise margins must be large enough for safe operation.
The disclosed method solves all of these problems without
the need for an additional power supply, and without any DC current path at the
The disclosed method uses a circuit for a 5V tolerant I/O
input buffer, which separates the propagation path of the high and low voltages
and protects the MOS devices without noise margin impacts. The circuit is
designed using a single high voltage (i.e. 3.3V) power supply.
The attached circuit, which is used for a 5V tolerant I/O
with 2.5V tolerant transistors, can also be used with minor changes for
low-voltage technology when high-voltage tolerance is needed.
Figure 1 shows the disclosed method when the circuit
receives the 5.5V, and translates it to the low voltage domain. In this
configuration, the Nbias is used to protect the NMOS devices from the high
input voltage, while the Pbias is used to protect the PMOS devices from the
high power supply voltage.