Browse Prior Art Database

Method to Measure On-Chip Power Supply Voltage Disclosure Number: IPCOM000028514D
Original Publication Date: 2004-May-18
Included in the Prior Art Database: 2004-May-18
Document File: 4 page(s) / 119K

Publishing Venue



The paper describes a successfully proven quantitative Method of local on-chip power supply voltage measurement. It utilizes randomly available quiet chip output circuits (signal drivers) to access the local on-chip power supply distribution network. The absolute differential power supply voltage measurement is a 2 step process, which eliminates any common mode on-chip noise as well as any externally coupled noise. The described scaling method allows to get true differential on-chip power supply voltage readings.

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DE820020053 Wolfgang Kauffmann/Germany/IBM Roland Frech, Andreas Huber, Erich Klink, Jochen Supper

Method to Measure On -

-Chip Power Supply Voltage

Chip Power Supply Voltage

Actual situation / Problem description

CMOS circuit technology of today and its application in large, highly synchronously switching digital VLSI chips requieres on chip power supply networks with high frequency current demands. These power supply current changes generate noise voltages on the power supply rails, which jeopardize the chip function. Therefore one of the main challenges in designing an appropriate on chip power distribution network system is keeping its high frequency noise behavior within predictable bounds under worst case conditions. On chip power supply measurements are beside proper simulation absolutely necessary to assure design quality.

Today's methods to solve the measurement problem

    To measure on chip power supply noise an appropriate chip switching activity is necessary to generate noise and there must be a meansfor HF voltage probing the on chip power supply VDD and VSS rails at various locations during the switching activity. The actual local on chip power supply voltage is the difference between VDD and VSS.

    One method is to measure on chip noise during wafer testing . But this situation does not represent a real system application and probing has do done with needles, which have very limited HF signal properties.

    A second method needs to implement special (differential) wiring through the chip carrier to the on chip power rails. These special signal lines have to be probed during system operation to measure the on chip power supply voltage. The line placement has to be done very carefully to avoid coupled noise on the path between chip and probing point, because there is no possibility to separate externally coupled noise from the on chip generated power supply noise.

New problem solution method

    The invention relates to a method which allows to measure the on chip power supply voltage at randomly selectable locations during system operation. Probing typically can be done at the signal interconnection between chip carrier and card/board. The measurement signal evaluation procedure removes externally coupled noise and the external signal reference level.

  Two facts are the key of the invention: Taking into account the CMOS technology properties, each non switching high speed off chip driver provides a high frequency path to the local on chip VDD and VSS power supply network (figure 1 & 2). The off chip signal wiring meets typically HF requirements. Taking into account the properties of the LSSD chip design methodology, it is possible to force any output driver into a static up or down level without impacting other functions. This allows to use selected output drivers temporarily for other purposes.


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