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Backside Infrared Microscopy for Lithographic Alignment of Opaque Metal Levels applied to MRAM Fabrication Disclosure Number: IPCOM000028520D
Original Publication Date: 2004-May-18
Included in the Prior Art Database: 2004-May-18
Document File: 6 page(s) / 256K

Publishing Venue



Magnetic Random Access Memories using the Tunnel Magnetoresistance phenomenon are attracting concerted scientific attention. Their fabrication requires deep sub-micron lithographic alignment of Magnetic Tunnel Junctions to underlying wiring. Compared to traditional VLSI integration, this application poses problems due to the opacity of the MTJ stack and hardmask to light used in alignment for most commercial steppers. We disclose herein a technique of backside alignment using infrared light as an enabler to a two step patterning process.

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Backside Infrared Microscopy for Lithographic Alignment of Opaque Metal Levels applied to MRAM Fabrication


     Magnetic Random Access Memories (MRAM) have been proposed as a universal memory of the future. They capture the salient features of several other memory technologies. Their densities, speed, non-volatility, infinite endurance and low-power consumption are not captured by any one single competitor [1]. MRAM falls in the category of Back End of Line (BEOL) memories where the Magnetic Tunnel Junction (MTJ) stack is deposited and patterned between two lines of metallization (Bitline at the Top and Word Line at the Bottom of the MTJ) in the BEOL. The MTJs are placed at the intersection of the mutually perpendicular successive levels of metallization. On the other hand, the transistors used to address and switch them are fabricated in the Front End of Line (FEOL)[2-3].

     For the Write operation, the reduction in the threshold of bitline (BL) current required to switch by the passage of current through the underlying wordline (WL) is crucial for operation of MTJs in larger arrays. This allows programming a bit by biasing the BL and WL that intersect at the TJ while not disturbing the other bits in the same row and column. The biasing requires that the currents be carefully set as to operate within the narrow margin outside the Astroid curve [4]. This margin for writing is reduced if the offset between the TJs and their wiring would vary within or across lots.

     It is the Read operation that distinguishes the two flavor of MRAM; Field effect Transistor assisted Read (FET) and the Cross-point cell (XPC). The FET cell, isolates the MTJ during the write operation and connects only the selected MTJ during the read operation through the local interconnect and contact via to the underlying CMOS. By contrast, the MTJs remain connected to the word and bitlines all the time during both operations in the XPC MRAM. (see Fig. 1)

TJ to Wordline Alignment Issues

     Integration schemes in literature describe the non-magnetic elements (FEOL Transistors and support circuitry) as being integrated up to the contact via level using conventional VLSI fabrication . This is followed by the deposition of blanket MTJs stack [1,4]. Lithographic alignment of the TJs to the underlying WLs is now required. This alignment, already constrained by the write margin considerations discussed above, is exacerbated by the opacity of the MTJ stack. The stepper is devoid of direct optical access to the alignment marks in the metallization level containing the WLs. (See Fig. 1)


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     Using the topography from contact via level surmounts this problem in the FET integration scheme. This solution is however fraught with two major drawbacks. The contact vias are aligned to the WL level. Aligning the TJs to the contact vias level only achieves second order alignment between the TJs and the WL. This increases the standard deviation in the TJ to WL offset by 40% ove...