Browse Prior Art Database

A Vestigially Extrapolated Via For Local Interconnection in MRAM FET Fabrication

IP.com Disclosure Number: IPCOM000028521D
Original Publication Date: 2004-May-18
Included in the Prior Art Database: 2004-May-18

Publishing Venue

IBM

Abstract

The 1T1J (1 Transistor and 1 Tunnel Junction) architecture for Magnetic Random access memories required Back-End of Line integration of Magnetic Tunnel Junctions (MTJ) to CMOS transistors. A local interconnect straps and contact via connect the tunnel junction to the CMOS front end. The via level is critical in that it typically precedes MTJ stack deposition and hence becomes the substrate for the Tunnel Junction (TJ). Reliability and cost could be improved by an alternate mechanism. We propose to that effect, an integration scheme where the via is constructed after the MTJ module.