OLED Display Luminance Control
Publication Date: 2004-May-24
The IP.com Prior Art Database
OLED Display Luminance Control
Luminance control for OLED displays has been demonstrated by controlling the time in which current is allowed to pass to the LED. However in certain applications (e.g. Avionics) the range of luminance required is extremely large and therefore special measures need to be taken. In this proposal addressing techniques, array structure and pixel circuits are proposed to address this issue.
Figure 1 shows two standard AMOLED pixel circuits. When T1 is on the storage capacitor C is charged to storage a gate source voltage for the drive TFT TD. In (b) T2 if off when T1 is on so that no current flows through the pixel when it is addressed. If the power line runs parallel to the address line A1 then this will stop corruption of the data voltage stored on C caused by power line voltage drops.
Figure 1 – Basic AMOLED pixel circuit.
In case (a) luminance control can be achieved by flashing the cathode and in case (b) by the on time of T2. Due to the luminance range required by certain applications i.e. avionics where the luminance range can be >1000 Cd/m2 to < 0.1Cd/m2 special measures need to be taken. Note that we need all grey scales within these luminance ranges e.g. 6-bits of data at 1000Cd/m2 as well as 0.1Cd/m2, so standard amplitude modulation cannot be employed.
When pulsing the cathode to achieve luminance control all pixel must be addressed when the cathode is high and then the cathode is brought low for a given time to achieve a certain luminance. A difficulty with this method is the displacement currents that can occur on a medium size display. For example the capacitance per unit area of PLED is 3.7x10-4 F/m2 so over a display of 4” by 3” i.e. 7.5x10-3m2 gives a capacitance of 2.8mF. If we take 35% as the aperture the actual capacitance is about 1mF. If the cathode swing is 10V, and this occurs in 1 msec then Idis = 10A. However switching over 100msecs gives 0.1A that is acceptable. However, when very low luminance is required the cathode on-time can be very short e.g. 20msecs, therefore the switching time must be at most 1 msec, so we will always have the problem of large displacement currents when switching the cathode in this particular application.
To avoid the possibility of large displacement currents induced by cathode switching the circuit of figure 1(b) should be used. In the present application it is preferable to arrange the circuit in figure 1(b) so that the power supply line is constructed using the lowest resistance metal (i.e. source-drain metal) because large currents can be drawn when the maximum luminance is required. For a landscape display this will mean the most effective array arrangement will be to have column and power lines running vertically (short axis) in low resistance metal and the address lines running horizontally (long axis) in the higher resistance metal. In this case shutting off T2 at the addressing time whilst other pixels are illum...