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Control Protocol for Arbitrated Crossbar Packet Switches Disclosure Number: IPCOM000028815D
Original Publication Date: 2004-Jun-03
Included in the Prior Art Database: 2004-Jun-03
Document File: 9 page(s) / 144K

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Control Protocol for Arbitrated Crossbar Packet Switches

Main Idea


The idea relates to the field of packet switching, specifically the field of input-queued packet-switch architectures. Many packet switches are based on an input-queued architecture, comprising queues sorted per output (virtual output queues - VOQ) at every line card, a crossbar routing fabric, and a central arbitration unit that computes which input is allowed to send to which output in every time slot. Typically, the arbiter is physically located close to the crossbar. It is distinguished between a data path , which comprises the flow of data packets from input line cards through the crossbar and to the output line cards, and a control path , which comprises the flow of control information from the line cards to the arbiter (e.g. requests) and back to the line cards (e.g. grants).

In practical large-capacity packet switches, there may be a significant physical distance between the line cards and the switch core. This distance translates to a round trip (RT) latency that can easily be many times larger than the packet duration, because the line rates have increased and the physical system size has grown, but the packet size has remained relatively constant.

The RT issue presents a new challenge in switch design, specifically for the control path, which must ensure efficient operation with minimal overhead.

State of the art

In existing approaches [1], each line card sends a request vector of N bits to the arbiter in every time slot where N is the number of switch ports. The j-th bit of the vector sent by input i indicates that the corresponding VOQ of input i for output j is not empty, i.e., it requests service for output j. This approach has the following drawbacks: first, the overhead is high, namely N*N bits in total. Second, it has been shown (see [3]) that this method leads to drastic throughput degradation under non-uniform traffic conditions when the control-path round trip is larger than the packet duration.

In [2] a method to physically distribute line cards and switch core is proposed, as illustrated in Fig. 5. This is achieved by means of a protocol (LCS) that enables lossless communication between the line cards and the switch ports, which comprise the VOQs. The switch ports are located close to the crossbar and the arbiter in order to minimize the RT between the VOQs and the arbiter. The bulk of the buffering and packet handling is performed in the line cards. The main drawback of this approach is that the line cards as well as the switch ports contain buffers, even though only a small amount of buffering, namely enough packets to cover one RT, is required in the switch ports. These buffered switch ports add cost, card space and electrical power, and they duplicate functionality already present in the line cards. Moreover, in the specific case of


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a switch core that comprises an optical routing fabric, these switch ports require...