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This invention allows the user to analyze Placement Driven Synthesis (PDS) results in real-time in a graphical view instead of waiting until the run is complete.
English (United States)
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Generation of quality of results data in a graphical format during placement driven synthesis optimization
The time and resources needed to build today's Application Specific Integrated Circuit (ASIC) designs is very dependent on the electronic design automation (EDA) software tools used. A Placement Driven Synthesis (PDS) tool optimizes a design for timing and area based on input constraints (timing constraints, die size, technology information, etc.) to minimize the time and resources required. Unfortunately, a single PDS process may take several days to complete. Current analysis of PDS runs occur post-process, so if an error occurs, it is not discovered until the end of the run and many hours or days will have been lost.
This invention allows the user to monitor the PDS process in real-time to determine the status (via an HTML output file) of the job. If something is wrong, the user is able to discover the error and possibly correct the error in real-time rather than waiting for the job to finish, thus saving time. The user can analyze slack, figure of merit (FOM), expanded figure of merit (eFOM), or any other information that PDS has the ability to store.
The proposed invention was not found while reviewing product literature from other leading physical synthesis vendor applications or existing U.S. patents.
PDS results are typically analyzed after the job is completed. The "Quality of Results" is stored in a log file and this file is parsed post-process to...